A Fast-Locking All-Digital Deskew Buffer with DCC using Digital-Controlled Delay Line

This paper presents a wide range fast lock all-digital deskew buffer using a digital controlled delay line, which achieves low jitter, fast lock, low power consumption and 50% duty cycle correction. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop. A balanced edge combiner to achieve 50% output clock is also presented. A circuit is designed in 0.18μm technology to demonstrate the feasibility of the proposed architecture with better figure of merit. The circuit can accept the input clock rates from 250 MHz to 1 GHz to generate close to output clocks with low jitter and phase noise. It owns the capability of closed loop power consumption.